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NJU26102
Digital Signal Processor for TV
General Description
Package
The NJU26102 is a digital signal processor that provides Delay, eala, ViVA2+, PEQ, and AGC. The NJU26102 is suitable for audio products such as TV, CD radio- cassette, speakers system, and others.
NJU26102FR1 Feature
* 3D Sound: eala, BBE ViVA, BBE ViVA+, BBE ViVA2+. * Sound enhancement: BBE, Mach3Bass. * 5band - PEQ, Tone Control. * AGC to control sound-volume difference between channels or programs.
Digital Signal Processor Specification
* 24bit Fixed-point Digital Signal Processing * Maximum System Clock Frequency : 38MHz * Digital Audio Interface : 3 Input ports / 3 Output ports * Master / Slave Mode * Master Mode MCK :1/2 fclk, 1/3 fclk ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs * Two kinds of micro computer interface I2C bus (standard-mode/100kbps) Serial interface (4 lines: clock, enable, input data, output data) * Power Supply : 2.5V ( 3.3V Input tolerant ) * Package : QFP32-R1 The detail hardware specification of the NJU26102 is described in the " NJU26100 Series Hardware Data Sheet".
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NJU26102
DSP Block Diagram
Fig.1 NJU26102 DSP Block Diagram
AD1/SDIN AD2/SSb
NJU26102
DSP ARITHMETIC UNIT SERIAL AUDIO INTERFACE BCKO LRO 24-BIT x 24-BIT MULTIPLIER ALU L/R SDO0~ SDI2 SDI0~ SDO2 BCKI
SCL/SCK
SDA/SDOUT
SERIAL HOST INTERFACE
PROGRAM CONTROL
RESETb MCK XI XO TIMING GENERATOR ADDRESS GENERATION UNIT
LRI
DELAY RAM
DATA RAM
FIRMWARE ROM
GPIO AND CONFIGURATION INTERFACE
SEL1
Function Block Diagram
Fig.2 NJU26102 Function Block Diagram
SW2 SDI0 SW1 SDO0 SDO1
Delay
SDI1 Trim SW4 SW3 SDI2 SW5 SW6 SW 7
3D
Enhancement
EQ
eala(stereo) AGC *1 Simulated Stereo BBE ViVA (3D, BBE)
BBE
BBE Mach3 Bass
AGC *2
5Band PEQ HPF + 4PEQ T.C. + 3PEQ HPF+T.C. +2PEQ
SW8
BBE ViVA+ (3D, BBE, Mach3Bass) BBE ViVA2+ (3D, BBE, Mach3Bass, AGC)
Master Vol.
SW10
SDO2
AGC *3 Note 1. only one AGCs(*1, *2, *3) should be used. Note 2. Do not use *1AGC and *3AGC during BBE ViVA2 being in use.
SW9
Continuous Siginal Det.
WDC
CLOCK GENERATOR
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NJU26102
Pin Configuration
VDDR VDDR VDDC VDDC VSSR
24
VSSR
23
VSSC
VSSC
22
21
20
19
18
17
SDI0 SDI1 SDI2 LRI BCKI MCK BCKO LRO
25
WDC VSSC VDDC RESETb VSSO XO XI VDDO
16
26 15 27 14 28
NJU26102
13
29 30 31 32 1
12 11 10 9
2
3
4
5
6
7
8
SDO0
SEL1
SCL/SCK
SDA/SDOUT
AD1/SDIN
AD2/SSb
SDO2
Fig.3 NJU26102 Pin Configuration
SDO1
Pin Description
Table 1 Pin Description
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol SDO2 SDO1 SDO0 SEL1 SCL/SCK SDA/SDOUT AD1/SDIN AD2/SSb VDDO XI XO VSSO RESETb VDDC VSSC WDC I/O O O O I *2 I I/O I I -I O -I --O *2 Description Audio Data Output 2 L/R Audio Data Output 1 L/R Audio Data Output 0 L/R Select I2C or Serial bus I2C Clock / Serial Clock I2C I/O / Serial Output I2C Address / Serial Input I2C Address / Serial Enable OSC Power Supply +2.5V X'tal Clock Input OSC Output OSC GND RESET (active Low) Core Power Supply +2.5V Core GND Clock for Watch Dog Timer No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol VDDC VDDC VSSC VSSC VDDR VDDR VSSR VSSR SDI0 SDI1 SDI2 LRI BCKI MCK BCKO LRO I/O --------I I I I I O O O Description Core Power Supply +2.5V Core Power Supply +2.5V Core GND Core GND I/O Power Supply +2.5V I/O Power Supply +2.5V I/O GND I/O GND Audio Data Input 0 L/R Audio Data Input 1 L/R Audio Data Input 2 L/R LR Clock Input Bit Clock Input Master Clock Output Bit Clock Output LR Clock Output
*1 I : Input, O : Output, I/O : Bi-directional *2 SEL1 : Input, WDC : Output
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NJU26102
Audio Interface
The NJU26102 audio interface provides industry serial data formats of I2S, MSB-first left-justified or MSB-first Right-justified. The NJU26102 audio interface provides three data inputs, SDI0, SDI1, and SDI2, and three data outputs, SDO0, SDO1, and SDO3, as shown in table 2 and 3. The input serial data is selected by the firmware command.
Table 2
Pin No. 25 26 27
Serial Audio Input Pin
Symbol SDI0 SDI1 SDI2 Description Audio Data Input 0 L / R Audio Data Input 1 L / R Audio Data Input 2 L / R
Table 3
Pin No. 3 2 1
Serial Audio Output Pin
Symbol SDO0 SDO1 SDO2 Description Audio Data Output 0 L / R Audio Data Output 1 L / R Audio Data Output 2 L / R
Host Interface
The NJU26102 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : 4-Wire serial bus or I2C bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data transfers, regardless of the chosen communication protocol. The detail 4-Wire Serial bus and I2C bus information are described in the " NJU26100 Series Hardware Data Sheet".
I2C address
AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. These pins offer additional flexibility to SLAVE address. 4 addresses could be chosen by AD1 and AD2-pin. The AD1 and AD2-pin addresses are decided by the connections of AD1 and AD2-pin. The AD1 and AD2 addresses should be the same level as AD1 and AD2-pin connections. Table 4 I2C Bus SLAVE Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 * * 0 0 1 1 1 AD2 AD1 R/W * AD1 or AD2 address is 0 when AD1 or AD2-pin is "L". AD1 or AD2 address is 1 when AD1 or AD2-pin is "H". The detail I2C bus timing of the NJU26102 is described in the " NJU26100 Series Hardware Data Sheet".
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NJU26102
Watchdog Clock
NJU26102 outputs clock pulse through WDC (Pin No. 16) during normal operation. WDC Clock Cycle (L / H) Time 184msec(fs=48kHz) 200msec(fs=44.1kHz) 276msec(fs=32kHz) The NJU26102 generates a clock pulse through the WDC terminal after resetting the NJU26102. The WDC clock is useful to check the status of the NJU26102 operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26102. When the WDC clock pulse is lost or not normal clock cycle, the NJU26102 does not operate correctly. Then reset the NJU26102 and set up the NJU26102 again.
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NJU26102
Firmware Command Table
Host processor can control the NJU26102 via 4-Wire serial bus or I2C bus interface. The following table summarizes the available user commands. Table 5 NJU26102 Command
No. 1 2 3 4 5 6 7 8 Command System State Firmware Version Request Firmware Mode Select Input Select / Fs Select Input Trim Master Volume Channel Balance AGC Threshold Level Command Description DSP Mode, Data Width, Serial Audio Mode, Audio Clock, MCK clock No. Firmware Version No. Request eala, BBE, Mach3Bass, ViVA, ViVA+, ViVA2, PEQ, AGC, Signal Detect, Bypass Input Select: SDI0, SDI1, SDI2, Delay Input Select Sample Rate: 48, 44.1, 32kHz 0 to -31dB 0 to -96dB, -Inf (with Smooth Control) 0 to -30dB, -Inf, L/R Select Threshold Level: -6 to -40dBFS Noise Compressor Threshold Level: -50 to -96dBFS, -Inf Attack Time: 0.1, 0.2, 0.5, 1, 2, 5sec Release Time: 1, 2, 5msec Ratio: 1.5:1, 2:1, 4:1, 8:1, 20:1, -Inf:1 Boost: 0 to +24dB Output Trim: 0 to -31dB Position: forward the 3D, EQ, backward the Master Volume 0 to +12dB 0 to +6dB Level: 0 to -15dB HF Adjust: 0 to 15 Threshold Level: -6 to -26dBFS Attack Time: 0.1, 0.2, 0.5, 1, 2, 5sec Release Time: 1, 2, 5msec Ratio: 2:1, 4:1, 8:1, -Inf:1 Boost: 0 to +24dB Output Trim: 0 to -31dB f0: 40 to 150Hz Q: 1.8 to 8.2 Gain: 0 to +12dB 5band PEQ, HPF, Tone Control f0: 20 to 20kHz(1/6 octave, 20 points/decade) Q: 0.33 to 8.2 Gain: -12 to +12dB Delay: 0 to 37.5msec (at Fs = 32kHz) Continuous Signal Detect No Operation
9 10 11 12
eala Gain BBE ViVA / ViVA+ Surround Gain BBE BBE ViVA2+ AGC
13
BBE Mach3Bass
14 15
EQ Mode PEQ f0 /HPF fc
16 17 18
Delay Time Continuous Signal Detect NOP
In respect to detail command information, request NJR.
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Ver.2004-08-26
NJU26102
License Information
1. The NJU26102 is manufactured by New Japan Radio Co.,Ltd. under license from BBE Sound Inc. BBE is a registered trademark of BBE Sound Inc. A license from BBE Sound Inc. must be required before the NJU26102 can be purchased from New Japan Radio Co.,Ltd. BBE Sound, Inc. 5831 Production Drive Huntington Beach, CA 92649 USA Tel: 714-897-6766 Fax: 714-896-0736
http://www.bbesound.com
2. Purchase of I2C components of New Japan Radio Co. ,Ltd or one of sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard specification as defined by Philips.
Version V1.1
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
Ver.2004-08-26
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